1. Field of the Invention
The present invention relates to a semiconductor part for component mounting, a mounting structure and a mounting method.
2. Description of Related Art
Strong demands have been made in recent years for portable electronic equipment such as digital cameras, digital portable telephones and notebook type personal computers that are thinner, are more compact and have lighter weight. Therefore, to what extent the surface mounting density of the semiconductor components used in the above devices can be increased has become an important technical issue.
To cope with this trend, the development of compact CSP (chip scale packages) typified by packaged ICs such as QFPs has progressed and some compact chip scale packages are now available.
These chip scale packages (CSP) incidentally, as can be seen from their other name of FP-BGA (Fine Pitch BGA) are designed for a compact BGA (Ball Grid Array) and their connection pin (hereafter called area terminals) array usually have an 0.8 mm pitch (BGA pitch is 1.27 mm.).
However, to cope with semiconductor LSI chips having higher density and more functions, the scope of the area terminal layout has shown a tend to continually increase and even the size of supposedly small CSP (chip scale packages) are becoming larger.
In order to allow these semiconductor LSI chips to handle a higher component mounting density by accommodating more pins, an even finer pitch is required in the area terminal array.
A chart of semiconductor assembly technology and mounting technology progress accompanying the miniaturization of semiconductor LSI devices is shown in Table 1 below. As can be seen, the number of area terminals has drastically increased to keep pace with higher density, systemization and miniaturization of semiconductor LSI devices. Table 1 also shows that in response to these developments, the CSP and BGA array pitch has become smaller and smaller.
Semiconductor TechnologyNumber ofconnectionpinsAluminumCSPBGADesign(general-electrodeterminalterminalYearscalepurpose)pitchpitchpitch19970.25 μm100-29580 μm500 μm1.27 μm19990.18 μm117-40070 μm400 μm1.27 μm20010.15 μm137-46960 μm400 μm1.00 μm20030.13 μm161-55150 μm300 μm1.00 μm20060.10 μm205-69950 μm300 μm0.80 μm
In a more specific description given while referring to the drawings, the CSP area terminals 1 and 2 are shown respectively in FIGS. 5A and 5B. A 0.8 mm pitch array is shown in FIG. 5A and a 0.5 mm pitch array is shown in FIG. 5B. In these figures, the reference numeral 20 denotes the (LSI) chip, 21 denotes a bonding wire, 22 denotes the plastic mold, and 23 denotes the bonding agent (adhesive).
Upon comparing these two pitch arrays in FIGS. 5A and 5B, it can be clearly observed that as the package size area terminal 2 becomes extremely small when the terminal array has a 0.5 mm pitch as shown in FIG. 5B.
FIG. 6 is a graph showing the correlation of package size and number of area terminal pins for each type of CSP used in portable telephones and handy digital video cameras on the market up till now. The graph shows package size increasing due to the trend to use a greater number of pins, and the package size shrinking from miniaturization with a 0.5 mm pitch array. In other words, the graph clearly shows that high density mounting is indispensable.
However, when miniaturizing the pitch array of area terminals in this way, reducing the size of the terminals is of course unavoidable. Even when mounting (connecting) chip scale packages (CSP) on boards, there is a large possibility of the connection strength deteriorating due to factors such as heat stress after mounting.
On the other hand, FIG. 7A shows the area terminals 1 arrayed with an 0.8 mm pitch on a CSP and at a 0.5 mm pitch in FIG. 7B along with the repositioned wiring 3 and 3a. As this figure clearly shows, more wiring is passing towards the inner side between the area terminals 1a and 1a rather than on the outermost side.
When the diameter of the area terminals of the 0.8 mm pitch array have for example been set to 0.4 mm, the L/S (line & space) for each wire is 30.8 μm (wiring pitch of 61.5 μm). However when the area terminal array is at a 0.5 mm pitch, and the diameter of the area terminals becomes an even smaller 0.25 mm, the wiring between those terminals have an L/S of 19.2 μm (wire pitch is 38.5 μm) so that obviously even finer wiring required.
Thus, when many wires are laid between the area terminals and the gap between the terminals becomes exceedingly small, then fine complex processing also becomes necessary on the board. For instance, use of built-up multilayer wiring board such as in the multilayering to rout the wiring 5 to the land terminal 4 is required as shown in FIGS. 8A and 8B.